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PPCRec: Fixes and optimizations + rework FRES/FRSQRTE
This commit is contained in:
Exzap
parent
89f8f9bd2a
commit
f94f99546d
13 changed files with 408 additions and 354 deletions
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@ -32,7 +32,7 @@ espresso_frsqrte_entry_t frsqrteLookupTable[32] =
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{0x20c1000, 0x35e},{0x1f12000, 0x332},{0x1d79000, 0x30a},{0x1bf4000, 0x2e6},
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};
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double frsqrte_espresso(double input)
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ATTR_MS_ABI double frsqrte_espresso(double input)
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{
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unsigned long long x = *(unsigned long long*)&input;
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@ -111,7 +111,7 @@ espresso_fres_entry_t fresLookupTable[32] =
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{0x88400, 0x11a}, {0x65000, 0x11a}, {0x41c00, 0x108}, {0x20c00, 0x106}
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};
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double fres_espresso(double input)
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ATTR_MS_ABI double fres_espresso(double input)
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{
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// based on testing we know that fres uses only the first 15 bits of the mantissa
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// seee eeee eeee mmmm mmmm mmmm mmmx xxxx .... (s = sign, e = exponent, m = mantissa, x = not used)
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@ -191,8 +191,8 @@ inline double roundTo25BitAccuracy(double d)
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return *(double*)&v;
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}
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double fres_espresso(double input);
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double frsqrte_espresso(double input);
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ATTR_MS_ABI double fres_espresso(double input);
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ATTR_MS_ABI double frsqrte_espresso(double input);
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void fcmpu_espresso(PPCInterpreter_t* hCPU, int crfD, double a, double b);
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@ -601,8 +601,10 @@ void PPCRecompilerX64Gen_imlInstruction_atomic_cmp_store(PPCRecFunction_t* PPCRe
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void PPCRecompilerX64Gen_imlInstruction_call_imm(PPCRecFunction_t* PPCRecFunction, ppcImlGenContext_t* ppcImlGenContext, x64GenContext_t* x64GenContext, IMLInstruction* imlInstruction)
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{
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// the register allocator takes care of spilling volatile registers and moving parameters to the right registers, so we don't need to do any special handling here
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x64GenContext->emitter->SUB_qi8(X86_REG_RSP, 0x28); // reserve enough space for any parameters while keeping stack alignment of 16 intact
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x64GenContext->emitter->MOV_qi64(X86_REG_RAX, imlInstruction->op_call_imm.callAddress);
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x64GenContext->emitter->CALL_q(X86_REG_RAX);
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x64GenContext->emitter->ADD_qi8(X86_REG_RSP, 0x28);
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}
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bool PPCRecompilerX64Gen_imlInstruction_r_r(PPCRecFunction_t* PPCRecFunction, ppcImlGenContext_t* ppcImlGenContext, x64GenContext_t* x64GenContext, IMLInstruction* imlInstruction)
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@ -780,18 +780,6 @@ void PPCRecompilerX64Gen_imlInstruction_fpr_r_r(PPCRecFunction_t* PPCRecFunction
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// move to FPR register
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x64Gen_movq_xmmReg_reg64(x64GenContext, regR, REG_RESV_TEMP);
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}
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else if( imlInstruction->operation == PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP )
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{
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// move register to XMM15
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x64Gen_movsd_xmmReg_xmmReg(x64GenContext, REG_RESV_FPR_TEMP, regA);
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// call assembly routine to calculate accurate FRES result in XMM15
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x64Gen_mov_reg64_imm64(x64GenContext, REG_RESV_TEMP, (uint64)recompiler_fres);
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x64Gen_call_reg64(x64GenContext, REG_RESV_TEMP);
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// copy result to bottom and top half of result register
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x64Gen_movddup_xmmReg_xmmReg(x64GenContext, regR, REG_RESV_FPR_TEMP);
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}
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else if (imlInstruction->operation == PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT)
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{
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// move register to XMM15
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@ -363,7 +363,6 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED ||
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operation == PPCREC_IML_OP_ASSIGN ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_NEGATE_PAIR ||
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operation == PPCREC_IML_OP_FPR_ABS_PAIR ||
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operation == PPCREC_IML_OP_FPR_FRES_PAIR ||
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@ -143,7 +143,6 @@ enum
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PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM, // leave top of destination untouched
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PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED,
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PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64, // expand bottom f32 to f64 in bottom and top half
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PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP, // calculate reciprocal with Espresso accuracy of source bottom half and write result to destination bottom and top half
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PPCREC_IML_OP_FPR_FCMPO_BOTTOM, // deprecated
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PPCREC_IML_OP_FPR_FCMPU_BOTTOM, // deprecated
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PPCREC_IML_OP_FPR_FCMPU_TOP, // deprecated
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@ -10,9 +10,16 @@
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#include <boost/container/static_vector.hpp>
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#include <boost/container/small_vector.hpp>
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#include "Common/cpu_features.h"
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#define DEBUG_RA_EXTRA_VALIDATION 0 // if set to non-zero, additional expensive validation checks will be performed
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#define DEBUG_RA_INSTRUCTION_GEN 0
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struct IMLRARegAbstractLiveness // preliminary liveness info. One entry per register and segment
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{
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IMLRARegAbstractLiveness(IMLRegFormat regBaseFormat, sint32 usageStart, sint32 usageEnd) : regBaseFormat(regBaseFormat), usageStart(usageStart), usageEnd(usageEnd) {};
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IMLRARegAbstractLiveness(IMLRegFormat regBaseFormat, sint32 usageStart, sint32 usageEnd)
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: regBaseFormat(regBaseFormat), usageStart(usageStart), usageEnd(usageEnd) {};
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void TrackInstruction(sint32 index)
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{
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@ -34,7 +41,6 @@ struct IMLRegisterAllocatorContext
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std::unordered_map<IMLRegID, IMLRegFormat> regIdToBaseFormat; // a vector would be more efficient but it also means that reg ids have to be continuous and not completely arbitrary
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// first pass
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std::vector<std::unordered_map<IMLRegID, IMLRARegAbstractLiveness>> perSegmentAbstractRanges;
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// second pass
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// helper methods
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inline std::unordered_map<IMLRegID, IMLRARegAbstractLiveness>& GetSegmentAbstractRangeMap(IMLSegment* imlSegment)
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@ -48,38 +54,117 @@ struct IMLRegisterAllocatorContext
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cemu_assert_debug(it != regIdToBaseFormat.cend());
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return it->second;
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}
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};
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struct IMLFixedRegisters
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{
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struct Entry
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{
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Entry(IMLReg reg, IMLPhysRegisterSet physRegSet) : reg(reg), physRegSet(physRegSet) {}
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Entry(IMLReg reg, IMLPhysRegisterSet physRegSet)
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: reg(reg), physRegSet(physRegSet) {}
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IMLReg reg;
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IMLPhysRegisterSet physRegSet;
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};
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boost::container::small_vector<Entry, 4> listInput; // fixed registers for instruction input edge
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boost::container::small_vector<Entry, 4> listOutput; // fixed registers for instruction output edge
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boost::container::small_vector<Entry, 4> listInput; // fixed register requirements for instruction input edge
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boost::container::small_vector<Entry, 4> listOutput; // fixed register requirements for instruction output edge
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};
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static void SetupCallingConvention(const IMLInstruction* instruction, IMLFixedRegisters& fixedRegs, const IMLPhysReg intParamToPhysReg[3], const IMLPhysReg floatParamToPhysReg[3], const IMLPhysReg intReturnPhysReg, const IMLPhysReg floatReturnPhysReg, IMLPhysRegisterSet volatileRegisters)
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{
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sint32 numIntParams = 0, numFloatParams = 0;
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auto AddParameterMapping = [&](IMLReg reg) {
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if (!reg.IsValid())
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return;
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if (reg.GetBaseFormat() == IMLRegFormat::I64)
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{
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IMLPhysRegisterSet ps;
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ps.SetAvailable(intParamToPhysReg[numIntParams]);
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fixedRegs.listInput.emplace_back(reg, ps);
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numIntParams++;
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}
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else if (reg.GetBaseFormat() == IMLRegFormat::F64)
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{
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IMLPhysRegisterSet ps;
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ps.SetAvailable(floatParamToPhysReg[numFloatParams]);
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fixedRegs.listInput.emplace_back(reg, ps);
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numFloatParams++;
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}
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else
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{
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cemu_assert_suspicious();
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}
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};
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AddParameterMapping(instruction->op_call_imm.regParam0);
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AddParameterMapping(instruction->op_call_imm.regParam1);
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AddParameterMapping(instruction->op_call_imm.regParam2);
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// return value
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if (instruction->op_call_imm.regReturn.IsValid())
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{
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IMLRegFormat returnFormat = instruction->op_call_imm.regReturn.GetBaseFormat();
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bool isIntegerFormat = returnFormat == IMLRegFormat::I64 || returnFormat == IMLRegFormat::I32 || returnFormat == IMLRegFormat::I16 || returnFormat == IMLRegFormat::I8;
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IMLPhysRegisterSet ps;
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if (isIntegerFormat)
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{
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ps.SetAvailable(intReturnPhysReg);
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volatileRegisters.SetReserved(intReturnPhysReg);
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}
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else
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{
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ps.SetAvailable(floatReturnPhysReg);
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volatileRegisters.SetReserved(floatReturnPhysReg);
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}
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fixedRegs.listOutput.emplace_back(instruction->op_call_imm.regReturn, ps);
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}
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// block volatile registers from being used on the output edge, this makes the register allocator store them during the call
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fixedRegs.listOutput.emplace_back(IMLREG_INVALID, volatileRegisters);
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}
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#if defined(__aarch64__)
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// aarch64
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static void GetInstructionFixedRegisters(IMLInstruction* instruction, IMLFixedRegisters& fixedRegs)
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{
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fixedRegs.listInput.clear();
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fixedRegs.listOutput.clear();
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// code below for aarch64 has not been tested
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// The purpose of GetInstructionFixedRegisters() is to constraint virtual registers to specific physical registers for instructions which need it
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// on x86 this is used for instructions like SHL <reg>, CL where the CL register is hardwired. On aarch it's probably only necessary for setting up the calling convention
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cemu_assert_unimplemented();
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#ifdef 0
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if (instruction->type == PPCREC_IML_TYPE_CALL_IMM)
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{
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const IMLPhysReg intParamToPhysReg[3] = {IMLArchAArch64::PHYSREG_GPR_BASE + 0, IMLArchAArch64::PHYSREG_GPR_BASE + 1, IMLArchAArch64::PHYSREG_GPR_BASE + 2};
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const IMLPhysReg floatParamToPhysReg[3] = {IMLArchAArch64::PHYSREG_FPR_BASE + 0, IMLArchAArch64::PHYSREG_FPR_BASE + 1, IMLArchAArch64::PHYSREG_FPR_BASE + 2};
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IMLPhysRegisterSet volatileRegs;
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for (int i=0; i<19; i++) // x0 to x18 are volatile
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volatileRegs.SetAvailable(IMLArchAArch64::PHYSREG_GPR_BASE + i);
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for (int i = 0; i <= 31; i++) // which float registers are volatile?
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volatileRegs.SetAvailable(IMLArchAArch64::PHYSREG_FPR_BASE + i);
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SetupCallingConvention(instruction, fixedRegs, intParamToPhysReg, floatParamToPhysReg, IMLArchAArch64::PHYSREG_GPR_BASE + 0, IMLArchAArch64::PHYSREG_FPR_BASE + 0, volatileRegs);
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}
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#endif
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}
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#else
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// x86-64
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static void GetInstructionFixedRegisters(IMLInstruction* instruction, IMLFixedRegisters& fixedRegs)
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{
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fixedRegs.listInput.clear();
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fixedRegs.listOutput.clear();
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// x86 specific logic is hardcoded for now
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if (instruction->type == PPCREC_IML_TYPE_R_R_R)
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{
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if (instruction->operation == PPCREC_IML_OP_LEFT_SHIFT || instruction->operation == PPCREC_IML_OP_RIGHT_SHIFT_S || instruction->operation == PPCREC_IML_OP_RIGHT_SHIFT_U)
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{
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// todo: We can skip this if g_CPUFeatures.x86.bmi2 is set, but for now we just assume it's not so we can properly test increased register pressure
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if(!g_CPUFeatures.x86.bmi2)
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{
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IMLPhysRegisterSet ps;
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_ECX);
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fixedRegs.listInput.emplace_back(instruction->op_r_r_r.regB, ps);
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}
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}
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}
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else if (instruction->type == PPCREC_IML_TYPE_ATOMIC_CMP_STORE)
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{
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IMLPhysRegisterSet ps;
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@ -88,38 +173,24 @@ static void GetInstructionFixedRegisters(IMLInstruction* instruction, IMLFixedRe
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}
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else if (instruction->type == PPCREC_IML_TYPE_CALL_IMM)
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{
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// parameters (todo)
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cemu_assert_debug(!instruction->op_call_imm.regParam0.IsValid());
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cemu_assert_debug(!instruction->op_call_imm.regParam1.IsValid());
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cemu_assert_debug(!instruction->op_call_imm.regParam2.IsValid());
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// return value
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if(instruction->op_call_imm.regReturn.IsValid())
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{
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IMLRegFormat returnFormat = instruction->op_call_imm.regReturn.GetBaseFormat();
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bool isIntegerFormat = returnFormat == IMLRegFormat::I64 || returnFormat == IMLRegFormat::I32 || returnFormat == IMLRegFormat::I16 || returnFormat == IMLRegFormat::I8;
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cemu_assert_debug(isIntegerFormat); // float return values are still todo
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IMLPhysRegisterSet ps;
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_EAX);
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fixedRegs.listOutput.emplace_back(instruction->op_call_imm.regReturn, ps);
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}
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// block volatile registers from being used on the output edge, this makes the RegAlloc store them during the call
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IMLPhysRegisterSet ps;
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if(!instruction->op_call_imm.regReturn.IsValid())
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_RAX);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_RCX);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_RDX);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_R8);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_R9);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_R10);
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ps.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE+X86_REG_R11);
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const IMLPhysReg intParamToPhysReg[3] = {IMLArchX86::PHYSREG_GPR_BASE + X86_REG_RCX, IMLArchX86::PHYSREG_GPR_BASE + X86_REG_RDX, IMLArchX86::PHYSREG_GPR_BASE + X86_REG_R8};
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const IMLPhysReg floatParamToPhysReg[3] = {IMLArchX86::PHYSREG_FPR_BASE + 0, IMLArchX86::PHYSREG_FPR_BASE + 1, IMLArchX86::PHYSREG_FPR_BASE + 2};
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IMLPhysRegisterSet volatileRegs;
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_RAX);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_RCX);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_RDX);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_R8);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_R9);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_R10);
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_GPR_BASE + X86_REG_R11);
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// YMM0-YMM5 are volatile
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for (int i = 0; i <= 5; i++)
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ps.SetAvailable(IMLArchX86::PHYSREG_FPR_BASE+i); // YMM0-YMM5 are volatile
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volatileRegs.SetAvailable(IMLArchX86::PHYSREG_FPR_BASE + i);
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// for YMM6-YMM15 only the upper 128 bits are volatile which we dont use
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fixedRegs.listOutput.emplace_back(IMLREG_INVALID, ps);
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SetupCallingConvention(instruction, fixedRegs, intParamToPhysReg, floatParamToPhysReg, IMLArchX86::PHYSREG_GPR_BASE + X86_REG_EAX, IMLArchX86::PHYSREG_FPR_BASE + 0, volatileRegs);
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}
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}
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#endif
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uint32 PPCRecRA_getNextIterationIndex()
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{
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@ -315,32 +386,6 @@ struct IMLRALivenessTimeline
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activeRanges.emplace_back(subrange);
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}
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// remove all ranges from activeRanges with end <= instructionIndex
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void ExpireRanges(sint32 instructionIndex)
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{
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__debugbreak(); // maybe replace calls with raInstructionEdge variant?
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expiredRanges.clear();
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size_t count = activeRanges.size();
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for (size_t f = 0; f < count; f++)
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{
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raLivenessRange* liverange = activeRanges[f];
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if (liverange->interval2.end.GetInstructionIndex() < instructionIndex) // <= to < since end is now inclusive
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{
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#ifdef CEMU_DEBUG_ASSERT
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if (instructionIndex != RA_INTER_RANGE_END && (liverange->subrangeBranchTaken || liverange->subrangeBranchNotTaken))
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assert_dbg(); // infinite subranges should not expire
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#endif
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expiredRanges.emplace_back(liverange);
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// remove entry
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activeRanges[f] = activeRanges[count-1];
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f--;
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count--;
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}
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}
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if(count != activeRanges.size())
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activeRanges.resize(count);
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}
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void ExpireRanges(raInstructionEdge expireUpTo)
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{
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expiredRanges.clear();
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@ -425,7 +470,10 @@ void PPCRecRA_MaskOverlappingPhysRegForGlobalRange(raLivenessRange* range2, IMLP
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}
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}
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bool _livenessRangeStartCompare(raLivenessRange* lhs, raLivenessRange* rhs) { return lhs->interval2.start < rhs->interval2.start; }
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bool _livenessRangeStartCompare(raLivenessRange* lhs, raLivenessRange* rhs)
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{
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return lhs->interval2.start < rhs->interval2.start;
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}
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void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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{
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@ -460,7 +508,7 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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subrangeList[i]->link_allSegmentRanges.next = subrangeList[i + 1];
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}
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// validate list
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#ifdef CEMU_DEBUG_ASSERT
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#if DEBUG_RA_EXTRA_VALIDATION
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sint32 count2 = 0;
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subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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raInstructionEdge currentStartPosition;
|
||||
|
|
@ -544,7 +592,7 @@ boost::container::small_vector<raLivenessRange*, 8> IMLRA_GetRangeWithFixedRegRe
|
|||
void IMLRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
|
||||
{
|
||||
// first pass - iterate over all ranges with fixed register requirements and split them if they cross the segment border
|
||||
// todo - this can be optimized. Ranges only need to be split if there are conflicts with other segments. Note that below passes rely on the fact that this pass currently splits all ranges with fixed register requirements
|
||||
// todo - this pass currently creates suboptimal results by splitting all ranges that cross the segment border if they have any fixed register requirement. This isn't always necessary
|
||||
for (raLivenessRange* currentRange = imlSegment->raInfo.linkedList_allSubranges; currentRange;)
|
||||
{
|
||||
IMLPhysRegisterSet allowedRegs;
|
||||
|
|
@ -608,7 +656,6 @@ void IMLRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment
|
|||
PPCRecRA_splitLocalSubrange2(ppcImlGenContext, range, entry.pos, true);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
// finally iterate ranges and assign fixed registers
|
||||
|
|
@ -626,7 +673,7 @@ void IMLRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment
|
|||
currentRange->SetPhysicalRegister(allowedRegs.GetFirstAvailableReg());
|
||||
}
|
||||
// DEBUG - check for collisions and make sure all ranges with fixed register requirements got their physical register assigned
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
#if DEBUG_RA_EXTRA_VALIDATION
|
||||
for (raLivenessRange* currentRange = imlSegment->raInfo.linkedList_allSubranges; currentRange; currentRange = currentRange->link_allSegmentRanges.next)
|
||||
{
|
||||
IMLPhysRegisterSet allowedRegs;
|
||||
|
|
@ -964,7 +1011,6 @@ private:
|
|||
} explodeRange;
|
||||
};
|
||||
|
||||
|
||||
class RASpillStrategy_ExplodeRangeInter : public RASpillStrategy
|
||||
{
|
||||
public:
|
||||
|
|
@ -1108,15 +1154,13 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
|
|||
raInstructionEdge currentRangeStart = subrangeItr->interval2.start; // used to be currentIndex before refactor
|
||||
PPCRecRA_debugValidateSubrange(subrangeItr);
|
||||
|
||||
// below used to be: std::min<sint32>(currentIndex, RA_INTER_RANGE_END-1)
|
||||
livenessTimeline.ExpireRanges((currentRangeStart > lastInstructionEdge) ? lastInstructionEdge : currentRangeStart); // expire up to currentIndex (inclusive), but exclude infinite ranges
|
||||
// note: The logic here is complicated in regards to whether the instruction index should be inclusive or exclusive. Find a way to simplify?
|
||||
|
||||
// if subrange already has register assigned then add it to the active list and continue
|
||||
if (subrangeItr->GetPhysicalRegister() >= 0)
|
||||
{
|
||||
// verify if register is actually available
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
#if DEBUG_RA_EXTRA_VALIDATION
|
||||
for (auto& liverangeItr : livenessTimeline.activeRanges)
|
||||
{
|
||||
// check for register mismatch
|
||||
|
|
@ -1176,8 +1220,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
|
|||
// cant assign register
|
||||
// there might be registers available, we just can't use them due to range conflicts
|
||||
RASpillStrategy* selectedStrategy = nullptr;
|
||||
auto SelectStrategyIfBetter = [&selectedStrategy](RASpillStrategy& newStrategy)
|
||||
{
|
||||
auto SelectStrategyIfBetter = [&selectedStrategy](RASpillStrategy& newStrategy) {
|
||||
if (newStrategy.GetCost() == INT_MAX)
|
||||
return;
|
||||
if (selectedStrategy == nullptr || newStrategy.GetCost() < selectedStrategy->GetCost())
|
||||
|
|
@ -1366,9 +1409,7 @@ raLivenessRange* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext& ctx
|
|||
}
|
||||
abstractRange->isProcessed = true;
|
||||
// create subrange
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
cemu_assert_debug(IMLRA_GetSubrange(imlSegment, vGPR) == nullptr);
|
||||
#endif
|
||||
cemu_assert_debug(
|
||||
(abstractRange->usageStart == abstractRange->usageEnd && (abstractRange->usageStart == RA_INTER_RANGE_START || abstractRange->usageStart == RA_INTER_RANGE_END)) ||
|
||||
abstractRange->usageStart < abstractRange->usageEnd); // usageEnd is exclusive so it should always be larger
|
||||
|
|
@ -1414,16 +1455,6 @@ raLivenessRange* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext& ctx
|
|||
PPCRecRA_convertToMappedRanges(ctx, it, vGPR, name);
|
||||
}
|
||||
}
|
||||
// for subranges which exit the segment at the end there is a hard requirement that they cover the suffix instruction
|
||||
// this is due to range load instructions being inserted before the suffix instruction
|
||||
// todo - currently later steps might break this assumption, look into this
|
||||
// if (subrange->interval2.ExtendsIntoNextSegment())
|
||||
// {
|
||||
// if (imlSegment->HasSuffixInstruction())
|
||||
// {
|
||||
// cemu_assert_debug(subrange->interval2.start.GetInstructionIndex() <= imlSegment->GetSuffixInstructionIndex());
|
||||
// }
|
||||
// }
|
||||
return subrange;
|
||||
}
|
||||
|
||||
|
|
@ -1432,8 +1463,7 @@ void IMLRA_ConvertAbstractToLivenessRanges(IMLRegisterAllocatorContext& ctx, IML
|
|||
{
|
||||
const std::unordered_map<IMLRegID, raLivenessRange*>& regToSubrange = IMLRA_GetSubrangeMap(imlSegment);
|
||||
|
||||
auto AddOrUpdateFixedRegRequirement = [&](IMLRegID regId, sint32 instructionIndex, bool isInput, const IMLPhysRegisterSet& physRegSet)
|
||||
{
|
||||
auto AddOrUpdateFixedRegRequirement = [&](IMLRegID regId, sint32 instructionIndex, bool isInput, const IMLPhysRegisterSet& physRegSet) {
|
||||
raLivenessRange* subrange = regToSubrange.find(regId)->second;
|
||||
cemu_assert_debug(subrange);
|
||||
raFixedRegRequirement tmp;
|
||||
|
|
@ -1624,8 +1654,12 @@ void PPCRecRA_followFlowAndExtendRanges(IMLRegisterAllocatorContext& ctx, IMLSeg
|
|||
list_segments.reserve(segmentCount + 1);
|
||||
list_processedSegment.resize(segmentCount);
|
||||
|
||||
auto markSegProcessed = [&list_processedSegment](IMLSegment* seg) {list_processedSegment[seg->momentaryIndex] = true; };
|
||||
auto isSegProcessed = [&list_processedSegment](IMLSegment* seg) -> bool { return list_processedSegment[seg->momentaryIndex]; };
|
||||
auto markSegProcessed = [&list_processedSegment](IMLSegment* seg) {
|
||||
list_processedSegment[seg->momentaryIndex] = true;
|
||||
};
|
||||
auto isSegProcessed = [&list_processedSegment](IMLSegment* seg) -> bool {
|
||||
return list_processedSegment[seg->momentaryIndex];
|
||||
};
|
||||
markSegProcessed(imlSegment);
|
||||
|
||||
sint32 index = 0;
|
||||
|
|
@ -1730,10 +1764,8 @@ void IMLRA_AnalyzeSubrangeDataDependency(raLivenessRange* subrange)
|
|||
subrange->_noLoad = true;
|
||||
}
|
||||
|
||||
|
||||
struct subrangeEndingInfo_t
|
||||
{
|
||||
//boost::container::small_vector<raLivenessSubrange_t*, 32> subrangeList2;
|
||||
raLivenessRange* subrangeList[SUBRANGE_LIST_SIZE];
|
||||
sint32 subrangeCount;
|
||||
|
||||
|
|
@ -1870,8 +1902,6 @@ inline IMLReg _MakeNativeReg(IMLRegFormat baseFormat, IMLRegID regId)
|
|||
return IMLReg(baseFormat, baseFormat, 0, regId);
|
||||
}
|
||||
|
||||
#define DEBUG_RA_INSTRUCTION_GEN 0
|
||||
|
||||
// prepass for IMLRA_GenerateSegmentMoveInstructions which updates all virtual registers to their physical counterparts
|
||||
void IMLRA_RewriteRegisters(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment)
|
||||
{
|
||||
|
|
@ -2036,7 +2066,6 @@ void IMLRA_GenerateSegmentMoveInstructions2(IMLRegisterAllocatorContext& ctx, IM
|
|||
// range expires
|
||||
// we cant erase it from virtId2PhysReg right away because a store might happen before the last use (the +1 thing above)
|
||||
|
||||
|
||||
// todo - check hasStore
|
||||
raLivenessRange* storedRange = *it;
|
||||
if (storedRange->hasStore)
|
||||
|
|
@ -2095,8 +2124,34 @@ void IMLRA_GenerateMoveInstructions(IMLRegisterAllocatorContext& ctx)
|
|||
}
|
||||
}
|
||||
|
||||
void DbgVerifyAllRanges(IMLRegisterAllocatorContext& ctx)
|
||||
static void DbgVerifyFixedRegRequirements(IMLSegment* imlSegment)
|
||||
{
|
||||
#if DEBUG_RA_EXTRA_VALIDATION
|
||||
std::vector<raFixedRegRequirementWithVGPR> frr = IMLRA_BuildSegmentInstructionFixedRegList(imlSegment);
|
||||
for(auto& fixedReq : frr)
|
||||
{
|
||||
for (raLivenessRange* range = imlSegment->raInfo.linkedList_allSubranges; range; range = range->link_allSegmentRanges.next)
|
||||
{
|
||||
if (!range->interval2.ContainsEdge(fixedReq.pos))
|
||||
continue;
|
||||
// verify if the requirement is compatible
|
||||
if(range->GetVirtualRegister() == fixedReq.regId)
|
||||
{
|
||||
cemu_assert(range->HasPhysicalRegister());
|
||||
cemu_assert(fixedReq.allowedReg.IsAvailable(range->GetPhysicalRegister())); // virtual register matches, but not assigned the right physical register
|
||||
}
|
||||
else
|
||||
{
|
||||
cemu_assert(!fixedReq.allowedReg.IsAvailable(range->GetPhysicalRegister())); // virtual register does not match, but using the reserved physical register
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void DbgVerifyAllRanges(IMLRegisterAllocatorContext& ctx)
|
||||
{
|
||||
#if DEBUG_RA_EXTRA_VALIDATION
|
||||
for (size_t s = 0; s < ctx.deprGenContext->segmentList2.size(); s++)
|
||||
{
|
||||
IMLSegment* imlSegment = ctx.deprGenContext->segmentList2[s];
|
||||
|
|
@ -2107,6 +2162,12 @@ void DbgVerifyAllRanges(IMLRegisterAllocatorContext& ctx)
|
|||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
}
|
||||
// check that no range validates register requirements
|
||||
for (size_t s = 0; s < ctx.deprGenContext->segmentList2.size(); s++)
|
||||
{
|
||||
DbgVerifyFixedRegRequirements(ctx.deprGenContext->segmentList2[s]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void IMLRegisterAllocator_AllocateRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLRegisterAllocatorParameters& raParam)
|
||||
|
|
@ -2121,7 +2182,7 @@ void IMLRegisterAllocator_AllocateRegisters(ppcImlGenContext_t* ppcImlGenContext
|
|||
IMLRA_CalculateLivenessRanges(ctx);
|
||||
IMLRA_ProcessFlowAndCalculateLivenessRanges(ctx);
|
||||
IMLRA_AssignRegisters(ctx, ppcImlGenContext);
|
||||
DbgVerifyAllRanges(ctx); // DEBUG
|
||||
DbgVerifyAllRanges(ctx);
|
||||
IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext);
|
||||
IMLRA_GenerateMoveInstructions(ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,9 +17,19 @@ public:
|
|||
m_regBitmask &= ~((uint64)1 << index);
|
||||
}
|
||||
|
||||
void SetAllAvailable()
|
||||
{
|
||||
m_regBitmask = ~0ull;
|
||||
}
|
||||
|
||||
bool HasAllAvailable() const
|
||||
{
|
||||
return m_regBitmask == ~0ull;
|
||||
}
|
||||
|
||||
bool IsAvailable(uint32 index) const
|
||||
{
|
||||
return (m_regBitmask & (1 << index)) != 0;
|
||||
return (m_regBitmask & ((uint64)1 << index)) != 0;
|
||||
}
|
||||
|
||||
IMLPhysRegisterSet& operator&=(const IMLPhysRegisterSet& other)
|
||||
|
|
|
|||
|
|
@ -67,38 +67,30 @@ boost::container::small_vector<raLivenessRange*, 128> raLivenessRange::GetAllSub
|
|||
return subranges;
|
||||
}
|
||||
|
||||
void raLivenessRange::GetAllowedRegistersExRecursive(raLivenessRange* range, uint32 iterationIndex, IMLPhysRegisterSet& allowedRegs)
|
||||
{
|
||||
range->lastIterationIndex = iterationIndex;
|
||||
for (auto& it : range->list_fixedRegRequirements)
|
||||
allowedRegs &= it.allowedReg;
|
||||
// check successors
|
||||
if (range->subrangeBranchTaken && range->subrangeBranchTaken->lastIterationIndex != iterationIndex)
|
||||
GetAllowedRegistersExRecursive(range->subrangeBranchTaken, iterationIndex, allowedRegs);
|
||||
if (range->subrangeBranchNotTaken && range->subrangeBranchNotTaken->lastIterationIndex != iterationIndex)
|
||||
GetAllowedRegistersExRecursive(range->subrangeBranchNotTaken, iterationIndex, allowedRegs);
|
||||
// check predecessors
|
||||
for (auto& prev : range->previousRanges)
|
||||
{
|
||||
if (prev->lastIterationIndex != iterationIndex)
|
||||
GetAllowedRegistersExRecursive(prev, iterationIndex, allowedRegs);
|
||||
}
|
||||
};
|
||||
|
||||
bool raLivenessRange::GetAllowedRegistersEx(IMLPhysRegisterSet& allowedRegisters)
|
||||
{
|
||||
if(interval2.ExtendsPreviousSegment() || interval2.ExtendsIntoNextSegment())
|
||||
{
|
||||
auto clusterRanges = GetAllSubrangesInCluster();
|
||||
bool hasAnyRequirement = false;
|
||||
for(auto& subrange : clusterRanges)
|
||||
{
|
||||
if(subrange->list_fixedRegRequirements.empty())
|
||||
continue;
|
||||
allowedRegisters = subrange->list_fixedRegRequirements.front().allowedReg;
|
||||
hasAnyRequirement = true;
|
||||
break;
|
||||
}
|
||||
if(!hasAnyRequirement)
|
||||
return false;
|
||||
for(auto& subrange : clusterRanges)
|
||||
{
|
||||
for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
|
||||
allowedRegisters &= fixedRegLoc.allowedReg;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// local check only, slightly faster
|
||||
if(list_fixedRegRequirements.empty())
|
||||
return false;
|
||||
allowedRegisters = list_fixedRegRequirements.front().allowedReg;
|
||||
for(auto& fixedRegLoc : list_fixedRegRequirements)
|
||||
allowedRegisters &= fixedRegLoc.allowedReg;
|
||||
}
|
||||
return true;
|
||||
uint32 iterationIndex = PPCRecRA_getNextIterationIndex();
|
||||
allowedRegisters.SetAllAvailable();
|
||||
GetAllowedRegistersExRecursive(this, iterationIndex, allowedRegisters);
|
||||
return !allowedRegisters.HasAllAvailable();
|
||||
}
|
||||
|
||||
IMLPhysRegisterSet raLivenessRange::GetAllowedRegisters(IMLPhysRegisterSet regPool)
|
||||
|
|
@ -424,6 +416,14 @@ void PPCRecRA_debugValidateSubrange(raLivenessRange* range)
|
|||
cemu_assert_debug(range->list_locations.front().index >= range->interval2.start.GetInstructionIndexEx());
|
||||
cemu_assert_debug(range->list_locations.back().index <= range->interval2.end.GetInstructionIndexEx());
|
||||
}
|
||||
// validate fixed reg requirements
|
||||
if (!range->list_fixedRegRequirements.empty())
|
||||
{
|
||||
cemu_assert_debug(range->list_fixedRegRequirements.front().pos >= range->interval2.start);
|
||||
cemu_assert_debug(range->list_fixedRegRequirements.back().pos <= range->interval2.end);
|
||||
for(sint32 i = 0; i < (sint32)range->list_fixedRegRequirements.size()-1; i++)
|
||||
cemu_assert_debug(range->list_fixedRegRequirements[i].pos < range->list_fixedRegRequirements[i+1].pos);
|
||||
}
|
||||
|
||||
}
|
||||
#else
|
||||
|
|
@ -563,7 +563,7 @@ raLivenessRange* PPCRecRA_splitLocalSubrange2(ppcImlGenContext_t* ppcImlGenConte
|
|||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (tailInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
||||
if (tailInterval.ContainsEdge(fixedReg->pos))
|
||||
{
|
||||
tailSubrange->list_fixedRegRequirements.push_back(*fixedReg);
|
||||
}
|
||||
|
|
@ -572,7 +572,7 @@ raLivenessRange* PPCRecRA_splitLocalSubrange2(ppcImlGenContext_t* ppcImlGenConte
|
|||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (!headInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
||||
if (!headInterval.ContainsEdge(fixedReg->pos))
|
||||
{
|
||||
subrange->list_fixedRegRequirements.resize(i);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -335,6 +335,9 @@ struct raLivenessRange
|
|||
void SetPhysicalRegister(sint32 physicalRegister);
|
||||
void SetPhysicalRegisterForCluster(sint32 physicalRegister);
|
||||
void UnsetPhysicalRegister() { physicalRegister = -1; }
|
||||
|
||||
private:
|
||||
void GetAllowedRegistersExRecursive(raLivenessRange* range, uint32 iterationIndex, IMLPhysRegisterSet& allowedRegs);
|
||||
};
|
||||
|
||||
raLivenessRange* PPCRecRA_createSubrange2(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, IMLRegID virtualRegister, IMLName name, raInstructionEdge startPosition, raInstructionEdge endPosition);
|
||||
|
|
|
|||
|
|
@ -181,9 +181,6 @@ PPCRecFunction_t* PPCRecompiler_recompileFunction(PPCFunctionBoundaryTracker::PP
|
|||
}
|
||||
}
|
||||
|
||||
// if(range.startAddress < 0x0202fa3C || range.startAddress > 0x0202FA7C)
|
||||
// return nullptr; // DEBUG
|
||||
|
||||
PPCRecFunction_t* ppcRecFunc = new PPCRecFunction_t();
|
||||
ppcRecFunc->ppcAddress = range.startAddress;
|
||||
ppcRecFunc->ppcSize = range.length;
|
||||
|
|
@ -340,15 +337,6 @@ bool PPCRecompiler_ApplyIMLPasses(ppcImlGenContext_t& ppcImlGenContext)
|
|||
//PPCRecompiler_reorderConditionModifyInstructions(&ppcImlGenContext);
|
||||
//PPCRecompiler_removeRedundantCRUpdates(&ppcImlGenContext);
|
||||
|
||||
|
||||
// if(ppcImlGenContext.debug_entryPPCAddress >= 0x0240B7F8 && ppcImlGenContext.debug_entryPPCAddress < 0x0240C0AC)
|
||||
// {
|
||||
// IMLDebug_Dump(&ppcImlGenContext);
|
||||
// __debugbreak();
|
||||
// }
|
||||
// else if(ppcImlGenContext.debug_entryPPCAddress >= 0x0240B7F8)
|
||||
// return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1513,7 +1513,7 @@ bool PPCRecompilerImlGen_DCBZ(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
|
|||
ppcImlGenContext->emitInst().make_r_r_r(PPCREC_IML_OP_ADD, regMemResEA, regA, regB);
|
||||
else
|
||||
ppcImlGenContext->emitInst().make_r_r(PPCREC_IML_OP_ASSIGN, regMemResEA, regB);
|
||||
ppcImlGenContext->emitInst().make_r_s32(PPCREC_IML_OP_AND, regMemResEA, ~31);
|
||||
ppcImlGenContext->emitInst().make_r_r_s32(PPCREC_IML_OP_AND, regMemResEA, regMemResEA, ~31);
|
||||
// zero out the cacheline
|
||||
for(sint32 i = 0; i < 32; i += 4)
|
||||
ppcImlGenContext->emitInst().make_memory_r(regZero, regMemResEA, i, 32, false);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,9 @@
|
|||
#include "PPCRecompilerIml.h"
|
||||
#include "Cafe/GameProfile/GameProfile.h"
|
||||
|
||||
ATTR_MS_ABI double frsqrte_espresso(double input);
|
||||
ATTR_MS_ABI double fres_espresso(double input);
|
||||
|
||||
IMLReg _GetRegCR(ppcImlGenContext_t* ppcImlGenContext, uint8 crReg, uint8 crBit);
|
||||
|
||||
void PPCRecompilerImlGen_generateNewInstruction_fpr_r_memory(ppcImlGenContext_t* ppcImlGenContext, IMLReg registerDestination, IMLReg registerMemory, sint32 immS32, uint32 mode, bool switchEndian, IMLReg registerGQR = IMLREG_INVALID)
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@ -1007,9 +1010,12 @@ bool PPCRecompilerImlGen_FRES(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
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// load registers
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IMLReg fprRegisterB = PPCRecompilerImlGen_loadFPRRegister(ppcImlGenContext, PPCREC_NAME_FPR0+frB);
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IMLReg fprRegisterD = PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext, PPCREC_NAME_FPR0+frD);
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PPCRecompilerImlGen_generateNewInstruction_fpr_r_r(ppcImlGenContext, PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP, fprRegisterD, fprRegisterB);
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ppcImlGenContext->emitInst().make_call_imm((uintptr_t)fres_espresso, fprRegisterB, IMLREG_INVALID, IMLREG_INVALID, fprRegisterD);
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// adjust accuracy
|
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PPRecompilerImmGen_optionalRoundBottomFPRToSinglePrecision(ppcImlGenContext, fprRegisterD);
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// copy result to top
|
||||
if( ppcImlGenContext->PSE )
|
||||
PPCRecompilerImlGen_generateNewInstruction_fpr_r_r(ppcImlGenContext, PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP, fprRegisterD, fprRegisterD);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1026,9 +1032,7 @@ bool PPCRecompilerImlGen_FRSP(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
|
|||
}
|
||||
PPCRecompilerImlGen_generateNewInstruction_fpr_r(ppcImlGenContext, NULL,PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM, fprRegisterD);
|
||||
if( ppcImlGenContext->PSE )
|
||||
{
|
||||
PPCRecompilerImlGen_generateNewInstruction_fpr_r_r(ppcImlGenContext, PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP, fprRegisterD, fprRegisterD);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1075,7 +1079,7 @@ bool PPCRecompilerImlGen_FRSQRTE(ppcImlGenContext_t* ppcImlGenContext, uint32 op
|
|||
// hCPU->fpr[frD].fpr = 1.0 / sqrt(hCPU->fpr[frB].fpr);
|
||||
IMLReg fprRegisterB = PPCRecompilerImlGen_loadFPRRegister(ppcImlGenContext, PPCREC_NAME_FPR0+frB);
|
||||
IMLReg fprRegisterD = PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext, PPCREC_NAME_FPR0+frD);
|
||||
PPCRecompilerImlGen_generateNewInstruction_fpr_r_r(ppcImlGenContext, PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT, fprRegisterD, fprRegisterB);
|
||||
ppcImlGenContext->emitInst().make_call_imm((uintptr_t)frsqrte_espresso, fprRegisterB, IMLREG_INVALID, IMLREG_INVALID, fprRegisterD);
|
||||
// adjust accuracy
|
||||
PPRecompilerImmGen_optionalRoundBottomFPRToSinglePrecision(ppcImlGenContext, fprRegisterD);
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue