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PPCRec: Some fixes
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commit
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2 changed files with 10 additions and 4 deletions
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@ -1000,7 +1000,8 @@ bool PPCRecompilerX64Gen_imlInstruction_r_r_r_carry(PPCRecFunction_t* PPCRecFunc
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auto regA = _reg32(imlInstruction->op_r_r_r_carry.regA);
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auto regA = _reg32(imlInstruction->op_r_r_r_carry.regA);
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auto regB = _reg32(imlInstruction->op_r_r_r_carry.regB);
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auto regB = _reg32(imlInstruction->op_r_r_r_carry.regB);
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auto regCarry = _reg32(imlInstruction->op_r_r_r_carry.regCarry);
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auto regCarry = _reg32(imlInstruction->op_r_r_r_carry.regCarry);
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cemu_assert_debug(regCarry != regR && regCarry != regA);
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bool carryRegIsShared = regCarry == regA || regCarry == regB;
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cemu_assert_debug(regCarry != regR); // two outputs sharing the same register is undefined behavior
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switch (imlInstruction->operation)
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switch (imlInstruction->operation)
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{
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{
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@ -1009,9 +1010,12 @@ bool PPCRecompilerX64Gen_imlInstruction_r_r_r_carry(PPCRecFunction_t* PPCRecFunc
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std::swap(regB, regA);
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std::swap(regB, regA);
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if (regR != regA)
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if (regR != regA)
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x64GenContext->emitter->MOV_dd(regR, regA);
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x64GenContext->emitter->MOV_dd(regR, regA);
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x64GenContext->emitter->XOR_dd(regCarry, regCarry);
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if(!carryRegIsShared)
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x64GenContext->emitter->XOR_dd(regCarry, regCarry);
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x64GenContext->emitter->ADD_dd(regR, regB);
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x64GenContext->emitter->ADD_dd(regR, regB);
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x64GenContext->emitter->SETcc_b(X86_CONDITION_B, _reg8_from_reg32(regCarry)); // below condition checks carry flag
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x64GenContext->emitter->SETcc_b(X86_CONDITION_B, _reg8_from_reg32(regCarry)); // below condition checks carry flag
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if(carryRegIsShared)
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x64GenContext->emitter->AND_di8(regCarry, 1); // clear upper bits
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break;
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break;
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case PPCREC_IML_OP_ADD_WITH_CARRY:
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case PPCREC_IML_OP_ADD_WITH_CARRY:
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// assumes that carry is already correctly initialized as 0 or 1
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// assumes that carry is already correctly initialized as 0 or 1
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@ -133,9 +133,11 @@ void PPCRecRARange_addLink_perVirtualGPR(std::unordered_map<IMLRegID, raLiveness
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else
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else
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{
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{
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// insert in first position
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// insert in first position
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subrange->link_sameVirtualRegister.next = it->second;
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raLivenessRange* priorFirst = it->second;
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subrange->link_sameVirtualRegister.next = priorFirst;
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it->second = subrange;
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it->second = subrange;
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subrange->link_sameVirtualRegister.prev = subrange;
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subrange->link_sameVirtualRegister.prev = nullptr;
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priorFirst->link_sameVirtualRegister.prev = subrange;
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}
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}
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}
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}
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