WIP web interface
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SergioFLS
parent
bbe02cc431
commit
98b7e9e80f
2 changed files with 136 additions and 90 deletions
178
dis.py
178
dis.py
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@ -50,93 +50,91 @@ def determine_instruction_type(opcode: int):
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else:
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return InstructionTypes.UNKNOWN
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OP = [int(argv[1],16), 0]
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if len(argv) >= 3:
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OP[1] = int(argv[2],16)
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match determine_instruction_type(OP[0]):
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case InstructionTypes.DATAPROCESSING_ALU6IMM:
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alu_op_fmt = {
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0b0000: 'R{0} += {1};',
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0b0001: 'R{0} += {1}, Carry;',
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0b0010: 'R{0} -= {1};',
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0b0011: 'R{0} -= {1}, Carry;',
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0b0100: 'CMP R{0}, {1};',
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0b0110: 'R{0} =- {1};',
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0b1000: 'R{0} ^= {1};',
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0b1001: 'R{0} = {1};',
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0b1010: 'R{0} |= {1};',
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0b1011: 'R{0} &= {1};',
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0b1100: 'TEST R{0}, {1};',
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}
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alu_op = (OP[0] & 0b1111_000_000_000000) >> 12
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rd = (OP[0] & 0b0000_111_000_000000) >> 9
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im6 = OP[0] & 0b0000_000_000_111111
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print(alu_op_fmt[alu_op].format(rd, im6))
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case InstructionTypes.DATAPROCESSING_ALU6DIR:
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alu_op_fmt = {
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0b0000: 'R{0} += [{1}];',
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0b0001: 'R{0} += [{1}], Carry;',
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0b0010: 'R{0} -= [{1}];',
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0b0011: 'R{0} -= [{1}], Carry;',
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0b0100: 'CMP R{0}, [{1}];',
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0b0110: 'R{0} =- [{1}];',
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0b1000: 'R{0} ^= [{1}];',
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0b1001: 'R{0} = [{1}];',
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0b1010: 'R{0} |= [{1}];',
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0b1011: 'R{0} &= [{1}];',
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0b1100: 'TEST R{0}, [{1}];',
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}
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alu_op = (OP[0] & 0b1111_000_000_000000) >> 12
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rd = (OP[0] & 0b0000_111_000_000000) >> 9
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a6 = OP[0] & 0b0000_000_000_111111
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print(alu_op_fmt[alu_op].format(rd, a6))
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case InstructionTypes.DATAPROCESSING_SHFT:
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shift_op_fmt = {
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0b000: '',
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0b001: 'ASR',
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0b010: 'LSL',
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0b011: 'LSR',
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0b100: 'ROL',
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0b101: 'ROR',
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}
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alu_op_fmt = {
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0b0000: 'R{0} += R{1} {2} {3};',
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0b0001: 'R{0} += R{1} {2} {3}, Carry;',
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0b0010: 'R{0} -= R{1} {2} {3};',
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0b0011: 'R{0} -= R{1} {2} {3}, Carry;',
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0b0100: 'CMP R{0}, R{1} {2} {3};',
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0b0110: 'R{0} =- R{1} {2} {3};',
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0b1000: 'R{0} ^= R{1} {2} {3};',
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0b1001: 'R{0} = R{1} {2} {3};',
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0b1010: 'R{0} |= R{1} {2} {3};',
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0b1011: 'R{0} &= R{1} {2} {3};',
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0b1100: 'TEST R{0}, R{1} {2} {3};',
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}
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alu_op = (OP[0] & 0b1111_000_0_000_00_000) >> 12
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rd = (OP[0] & 0b0000_111_0_000_00_000) >> 9
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shift_op = (OP[0] & 0b0000_000_0_111_00_000) >> 5
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n = (OP[0] & 0b0000_000_0_000_11_000) >> 3
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rs = OP[0] & 0b0000_000_0_000_00_111
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print(alu_op_fmt[alu_op].format(rd, rs, shift_op_fmt[shift_op], n+1))
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case InstructionTypes.INTERRUPT:
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irq = (OP[0] & 0b01) != 0
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fiq = (OP[0] & 0b10) != 0
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if irq and not fiq:
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print('INT IRQ;')
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elif not irq and fiq:
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print('INT FIQ;')
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elif irq and fiq:
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print('INT FIQ,IRQ;')
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else:
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print('INT OFF;')
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case InstructionTypes.FUNCTION_RETF:
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print('RETF;')
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case InstructionTypes.FUNCTION_RETI:
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print('RETI;')
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case _:
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print('unknown instruction')
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def disassemble(opcode: list):
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match determine_instruction_type(opcode[0]):
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case InstructionTypes.DATAPROCESSING_ALU6IMM:
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alu_op_fmt = {
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0b0000: 'R{0} += {1};',
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0b0001: 'R{0} += {1}, Carry;',
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0b0010: 'R{0} -= {1};',
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0b0011: 'R{0} -= {1}, Carry;',
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0b0100: 'CMP R{0}, {1};',
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0b0110: 'R{0} =- {1};',
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0b1000: 'R{0} ^= {1};',
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0b1001: 'R{0} = {1};',
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0b1010: 'R{0} |= {1};',
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0b1011: 'R{0} &= {1};',
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0b1100: 'TEST R{0}, {1};',
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}
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alu_op = (opcode[0] & 0b1111_000_000_000000) >> 12
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rd = (opcode[0] & 0b0000_111_000_000000) >> 9
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im6 = opcode[0] & 0b0000_000_000_111111
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return alu_op_fmt[alu_op].format(rd, im6)
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case InstructionTypes.DATAPROCESSING_ALU6DIR:
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alu_op_fmt = {
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0b0000: 'R{0} += [{1}];',
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0b0001: 'R{0} += [{1}], Carry;',
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0b0010: 'R{0} -= [{1}];',
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0b0011: 'R{0} -= [{1}], Carry;',
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0b0100: 'CMP R{0}, [{1}];',
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0b0110: 'R{0} =- [{1}];',
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0b1000: 'R{0} ^= [{1}];',
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0b1001: 'R{0} = [{1}];',
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0b1010: 'R{0} |= [{1}];',
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0b1011: 'R{0} &= [{1}];',
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0b1100: 'TEST R{0}, [{1}];',
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}
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alu_op = (opcode[0] & 0b1111_000_000_000000) >> 12
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rd = (opcode[0] & 0b0000_111_000_000000) >> 9
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a6 = opcode[0] & 0b0000_000_000_111111
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return alu_op_fmt[alu_op].format(rd, a6)
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case InstructionTypes.DATAPROCESSING_SHFT:
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shift_op_fmt = {
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0b000: '',
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0b001: 'ASR',
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0b010: 'LSL',
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0b011: 'LSR',
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0b100: 'ROL',
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0b101: 'ROR',
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}
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alu_op_fmt = {
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0b0000: 'R{0} += R{1} {2} {3};',
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0b0001: 'R{0} += R{1} {2} {3}, Carry;',
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0b0010: 'R{0} -= R{1} {2} {3};',
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0b0011: 'R{0} -= R{1} {2} {3}, Carry;',
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0b0100: 'CMP R{0}, R{1} {2} {3};',
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0b0110: 'R{0} =- R{1} {2} {3};',
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0b1000: 'R{0} ^= R{1} {2} {3};',
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0b1001: 'R{0} = R{1} {2} {3};',
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0b1010: 'R{0} |= R{1} {2} {3};',
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0b1011: 'R{0} &= R{1} {2} {3};',
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0b1100: 'TEST R{0}, R{1} {2} {3};',
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}
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alu_op = (opcode[0] & 0b1111_000_0_000_00_000) >> 12
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rd = (opcode[0] & 0b0000_111_0_000_00_000) >> 9
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shift_op = (opcode[0] & 0b0000_000_0_111_00_000) >> 5
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n = (opcode[0] & 0b0000_000_0_000_11_000) >> 3
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rs = opcode[0] & 0b0000_000_0_000_00_111
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return alu_op_fmt[alu_op].format(rd, rs, shift_op_fmt[shift_op], n+1)
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case InstructionTypes.INTERRUPT:
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irq = (opcode[0] & 0b01) != 0
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fiq = (opcode[0] & 0b10) != 0
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if irq and not fiq:
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return 'INT IRQ;'
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elif not irq and fiq:
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return 'INT FIQ;'
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elif irq and fiq:
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return 'INT FIQ,IRQ;'
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else:
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return 'INT OFF;'
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case InstructionTypes.FUNCTION_RETF:
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return 'RETF;'
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case InstructionTypes.FUNCTION_RETI:
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return 'RETI;'
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case _:
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return 'unknown instruction'
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48
index.html
Normal file
48
index.html
Normal file
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@ -0,0 +1,48 @@
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<!DOCTYPE html>
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<html>
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<head>
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<meta charset="utf-8"></meta>
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<!-- TODO probably use something else that doesn't use Cloudflare -->
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<script type="text/javascript" src="https://cdn.jsdelivr.net/npm/brython@3.12.2/brython.min.js"></script>
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<script type="text/javascript" src="https://cdn.jsdelivr.net/npm/brython@3.12.2/brython_stdlib.js"></script>
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<script type="text/python" src="./dis.py" id="unspdis"></script>
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<title>unsp-dasm</title>
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<script type="text/python">
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import browser
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import unspdis
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dis_input = browser.document['disassemble-input']
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dis_output = browser.document['disassemble-output']
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def hello(ev):
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args = []
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for value in dis_input.value.split(' '):
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args.append(int(value, 16))
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if len(args) == 1:
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args.append(0)
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dis_output.value = unspdis.disassemble(args)
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browser.document['disassemble-button'].bind('click', hello)
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</script>
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</head>
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<body style="font-family: sans-serif;">
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<h1>unsp-das</h1>
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<noscript>You seem to have JavaScript disabled. If you don't want to enable it, feel free to download the program below.</noscript>
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<div class="disassembler">
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<textarea id="disassemble-input" cols="20" rows="3" placeholder="93FF"></textarea>
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<textarea id="disassemble-output" cols="20" rows="3" disabled></textarea>
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<button id="disassemble-button">Disassemble</button>
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</div>
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<div class="info">
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<h2>What is this?</h2>
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<p>This is an personal attempt at creating a disassembler for the µ'nSP ISA created by Sunplus Technology.</p>
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<p>The µ'nSP architecture is an 16-bit CPU architecture that was used on microcontrollers and some plug-and-play video game devices (Such as the various Jakks Pacific GameKey-board consoles and the VTech V.Smile).</p>
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<p>This disassembler was written in Python and runs on the web using <a href="https://brython.info">Brython</a>.</p>
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<p>Source is available at <a href="https://git.nadeko.net/Serg2/unsp-dasm">git.nadeko.net/Serg2/unsp-dasm</a> and is licensed under the MIT No Attribution license.</p>
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</div>
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</body>
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</html>
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