From 146e5baa660513a4e7add37bd23f81a342269fb3 Mon Sep 17 00:00:00 2001
From: Amin Bandali <bandali@canonical.com>
Date: Fri, 1 Sep 2023 14:48:35 -0400
Subject: [PATCH] Update SaveContext/LoadContext via upstream patch

---
 debian/patches/series                         |  1 +
 .../update-savecontext-loadcontext.patch      | 54 +++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 debian/patches/update-savecontext-loadcontext.patch

diff --git a/debian/patches/series b/debian/patches/series
index 4607cd4..fcae278 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,3 +1,4 @@
+update-savecontext-loadcontext.patch
 update-vulkan-headers.patch
 fixes-for-gcc-13.patch
 # Upstreamable patches
diff --git a/debian/patches/update-savecontext-loadcontext.patch b/debian/patches/update-savecontext-loadcontext.patch
new file mode 100644
index 0000000..ab73728
--- /dev/null
+++ b/debian/patches/update-savecontext-loadcontext.patch
@@ -0,0 +1,54 @@
+From 9c94faaa2b2532a4d383afc1b9825bd5005e5a8e Mon Sep 17 00:00:00 2001
+From: bunnei <bunneidev@gmail.com>
+Origin: https://github.com/yuzu-emu/yuzu-mainline/commit/9c94faaa2b2532a4d383afc1b9825bd5005e5a8e
+Date: Sat, 1 Apr 2023 17:03:08 -0700
+Subject: [PATCH] core: arm_dynarmic_32: Update SaveContext/LoadContext.
+
+---
+ src/core/arm/dynarmic/arm_dynarmic_32.cpp | 23 ++++++++++-------------
+ 1 file changed, 10 insertions(+), 13 deletions(-)
+
+diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+index cab21a88e84c..dfdcbe35ac15 100644
+--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
++++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+@@ -5,7 +5,6 @@
+ #include <memory>
+ #include <dynarmic/interface/A32/a32.h>
+ #include <dynarmic/interface/A32/config.h>
+-#include <dynarmic/interface/A32/context.h>
+ #include "common/assert.h"
+ #include "common/literals.h"
+ #include "common/logging/log.h"
+@@ -410,21 +409,19 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
+ }
+ 
+ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
+-    Dynarmic::A32::Context context;
+-    jit.load()->SaveContext(context);
+-    ctx.cpu_registers = context.Regs();
+-    ctx.extension_registers = context.ExtRegs();
+-    ctx.cpsr = context.Cpsr();
+-    ctx.fpscr = context.Fpscr();
++    Dynarmic::A32::Jit* j = jit.load();
++    ctx.cpu_registers = j->Regs();
++    ctx.extension_registers = j->ExtRegs();
++    ctx.cpsr = j->Cpsr();
++    ctx.fpscr = j->Fpscr();
+ }
+ 
+ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
+-    Dynarmic::A32::Context context;
+-    context.Regs() = ctx.cpu_registers;
+-    context.ExtRegs() = ctx.extension_registers;
+-    context.SetCpsr(ctx.cpsr);
+-    context.SetFpscr(ctx.fpscr);
+-    jit.load()->LoadContext(context);
++    Dynarmic::A32::Jit* j = jit.load();
++    j->Regs() = ctx.cpu_registers;
++    j->ExtRegs() = ctx.extension_registers;
++    j->SetCpsr(ctx.cpsr);
++    j->SetFpscr(ctx.fpscr);
+ }
+ 
+ void ARM_Dynarmic_32::SignalInterrupt() {